Structure optimization of intelligent substation relay protection device based on SoC
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    Abstract:

    The protection installation mode and detection requirements in intelligent substation is enhanced, and the low reliability problem of previous protection system due to the slow transmission speed and the overly complex architecture need to be handled. In this paper, a k-means algorithm-based priority management method is proposed to divide and exchange the data, and to ensure the real-time performance of the data. The FPGA is used as the parallel communication coprocessor to enhance the transmission efficiency to the processor. Thus, a SoC chip protection device is developed. The operation time of the protection device is determined by the fault oscillogram of simulation by the RTDS, which can prove the reliability and practicability of the devices. Finally, the protection device is applied in some substations of Southern Power Grid for three years. The results show that the operation of the device is reliable and stable, the protection can therefore be localized, miniaturized, and the protection and power consumption can also be ameliorated.

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姚浩,习伟,陈浩敏,陈波,周涛,陈秋荣,徐万方.基于SoC的单芯片保护装置架构设计优化[J].电力科学与技术学报英文版,2021,36(5):20-27. Yao Hao, Xi Wei, Chen Haomin, Chen Bo, Zhou Tao, Chen Qiurong, Xu Wanfang. Structure optimization of intelligent substation relay protection device based on SoC[J]. Journal of Electric Power Science and Technology,2021,36(5):20-27.

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  • Received:
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  • Online: November 16,2021
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