Improving the working efficiency of power terminal chips while reducing their energy consumption is one of the research direction for optimizing smart grid systems. Aiming at the efficient management of cache data in MPSoC, the multi-processor shared cache partitioning technology is studied. The curve fitting technology is utilized to model the cache, and mathematical methods is incorporated to solve the CP problem. The mathematical expression of the energy consumption in subsystem can be obtained according to the mathematical relationship between the obtained missing rate curve of the shared cache and the energy consumption of the subsystem. Combined with the energy consumption model of the processor, the comprehensive optimal CP solution is generated. Experimental verification shows that the processor subsystem energy consumption can be reduced to 27.9% of the subsystem before optimization using this CP method.